The present invention relates generally to the design and fabrication of semiconductor integrated circuits, and more particularly to a method to achieve timing closure of a digital circuit design.
Very large integrated circuits, which are often referred to as systems-on-a-chip (SoCs), are designed by dividing the design into multiple modules. The modules are designed concurrently with coordination among the module design groups. Until the modules are stitched together, there is uncertainty as to whether the overall design will meet the specified design criteria, such as the frequency of operation and other timing constraints.
In some SoCs, a clock signal is generated by an oscillator and distributed throughout the SoC. When the clock signal, which may be routed on more than one metal layer of the integrated circuit, is distributed on a single conductor, referred to as a common path, variations on the common path influence the clock signal provided to the clock-signal-recipient components throughout the SoC. When the clock signal is distributed on a network of conductors, each bifurcation typically includes a buffer in each bifurcated branch conductor, which results in (i) a pre-bifurcation clock signal branch and (ii) each of the post-bifurcation clock signal branches having clock signals with slightly different variations. Thus, the clock signals provided to different clock-signal-recipient components throughout the SoC may be skewed. On-chip variations (OCV), such as process, voltage, and temperature (PVT) variations, compound clock signal variations. Clock signal variations are less tolerable in higher frequency applications due to the shorter clock period for signals to propagate. Accordingly, it would be advantageous to be able to test a SoC for clock signal variations.